As an external storage device used in a computer system, an SSD (Solid State Drive) mounted with a nonvolatile semiconductor memory such as a NAND-type flash memory attracts attention. The flash memory has advantages such as high speed and light weight compared with a magnetic disk device.
The SSD includes a plurality of flash memory chips, a controller that performs read/write control for the respective flash memory chips in response to a request from a host apparatus, a buffer memory for performing data transfer between the respective flash memory chips and the host apparatus, a power supply circuit, and a connection interface to the host apparatus (e.g., Patent Document 1).
Examples of the nonvolatile semiconductor memory include nonvolatile semiconductor memories in which a unit of erasing, writing, and readout is fixed such as a nonvolatile semiconductor memory that, in storing data, once erases the data in block units and then performs writing and a nonvolatile semiconductor memory that performs writing and readout in page units in the same manner as the NAND-type flash memory.
On the other hand, a unit for a host apparatus such as a personal computer to write data in and read out the data from a secondary storage device such as a hard disk is called sector. The sector is set independently from a unit of erasing, writing, and readout of a semiconductor storage device.
For example, whereas a size of a block (a block size) of the nonvolatile semiconductor memory is 512 kB and a size of a page (a page size) thereof is 4 kB, a size of a sector (a sector size) of the host apparatus is set to 512 B.
In this way, the unit of erasing, writing, and readout of the nonvolatile semiconductor memory may be larger than the unit of writing and readout of the host apparatus.
Therefore, when the secondary storage device of the personal computer such as the hard disk is configured by using the nonvolatile semiconductor memory, it is necessary to write data with a small size from the personal computer as the host apparatus by adapting the size to the block size and the page size of the nonvolatile semiconductor memory.
The data recorded by the host apparatus such as the personal computer has both temporal locality and spatial locality (see, for example, Non-Patent Document 1). Therefore, when data is recorded, if the data is directly recorded in an address designated from the outside, rewriting, i.e., erasing processing temporally concentrates in a specific area and a bias in the number of times of erasing increases. Therefore, in the NAND-type flash memory, processing called wear leveling for equally distributing data update sections is performed.
In the wear leveling processing, for example, a logical address designated by the host apparatus is translated into a physical address of the nonvolatile semiconductor memory in which the data update sections are equally distributed.
When a large-capacity secondary storage device is configured by using such a NAND flash memory, in performing the address translation, it is necessary to adapt small-sized data from the personal computer as the host apparatus to the block size and the page size of the nonvolatile semiconductor memory and write the data. In such data management, if a unit of the data management is a small size (e.g., the page size), the size of management tables increases and does not fit in a main memory of a controller of the secondary storage device. Address conversion cannot be performed at high speed. In a search through the management tables, if search processing takes long, an advantage of the flash memory that the flash memory is fast compared with a magnetic disk device cannot be effectively utilized. In this way, the size of the management tables inevitably increases according to an increase in capacity of the NAND flash memory as the secondary storage device. Therefore, there is a demand for a method of reducing a capacity of the management tables as much as possible and a method of increasing speed of the search processing for the management tables.    [Patent Document 1] Japanese Patent No. 3688835    [Non-Patent Document 1] David A. Patterson and John L. Hennessy, “Computer Organization and Design: The Hardware/Software Interface”, Morgan Kaufmann Pub, 2004 Aug. 31